View LTC1272_1343269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 LTC1272 12-bit, 3 m s, 250khz sampling a/d converter d u escriptio n ad7572 pinout n 12-bit resolution n 3 m s and 8 m s conversion times n on-chip sample-and-hold n up to 250khz sample rates n 5v single supply operation n no negative supply required n on-chip 25ppm/ c reference n 75mw (typ) power consumption n 24-pin narrow dip and sol packages n esd protected on all pins s f ea t u re n high speed data acquisition n digital signal processing (dsp) n multiplexed data acquisition systems n single supply systems u s a o pp l ic at i the LTC1272 is a 3 m s, 12-bit, successive approximation sampling a/d converter. it has the same pinout as the industry standard ad7572 and offers faster conversion time, on-chip sample-and-hold, and single supply opera- tion. it uses ltbicmos tm switched-capacitor technology to combine a high speed 12-bit adc with a fast, accurate sample-and-hold and a precision reference. the LTC1272 operates with a single 5v supply but can also accept the 5v/C15v supplies required by the ad7572 (pin 23, the negative supply pin of the ad7572, is not connected on the LTC1272). the LTC1272 has the same 0v to 5v input range as the ad7572 but, to achieve single supply opera- tion, it provides a 2.42v reference output instead of the C 5.25v of the ad7572. it plugs in for the ad7572 if the reference capacitor polarity is reversed and a 1 m s sample- and-hold acquisition time is allowed between conversions. the output data can be read as a 12-bit word or as two 8-bit bytes. this allows easy interface to both 8-bit and higher processors. the LTC1272 can be used with a crystal or an external clock and comes in speed grades of 3 m s and 8 m s. frequency (khz) 0 ?40 amplitude (db) 20 40 60 80 LTC1272 ?ta02 ?20 ?00 ?0 ?0 ?0 ?0 0 100 120 s (n+d) = 72.1 single 5v supply, 3 m s, 12-bit sampling adc 10 f m in ref d11 (msb) d10 d9 d8 d7 clk in clk out hben rd cs busy nc v LTC1272 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd p control lines m m 0.1 f 5v 8 or 12-bit parallel bus analog input (0v to 5v) 10 m f 0.1 m f LTC1272 ?ta01 + + 2.42v v output ref u a o pp l ic at i ty p i ca l ltbicmos is a trademark of linear technology corporation 1024 point fft, f s = 250khz, f in = 10khz
LTC1272 2 a u g w a w u w a r b s o lu t exi t i s supply voltage (v dd ) ................................................. 6v analog input voltage (note 3) ................... C 0.3v to 15v digital input voltage .................................. C 0.3v to 12v digital output voltage .................... C 0.3v to v dd + 0.3v power dissipation .............................................. 500mw operating temperature range LTC1272-xac, cc ................................. 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c (notes 1 and 2) wu u package / o rder i for atio consult factory for industrial and military grade parts. LTC1272-xa LTC1272-xc parameter conditions min typ max min typ max units resolution (no missing codes) l 12 12 bits integral linearity error (note 5) l 1/2 1 lsb differential linearity error l 1 1 lsb offset error 3 4 lsb l 4 6 lsb gain error 10 15 lsb full-scale tempco i out (reference) = 0 l 5 25 10 45 ppm/ c cc hara terist ics co u verter with internal reference (note 4) conversion conversion time = 3 m s time = 8 m s LTC1272-3acn LTC1272-8acn LTC1272-3ccn LTC1272-8ccn s package only LTC1272-3acs LTC1272-8acs LTC1272-3ccs LTC1272-8ccs 24 23 22 21 20 19 18 17 8 7 6 5 4 3 2 1 in ref (msb) d11 d10 d9 d8 d7 clk in clk out hben rd cs busy nc v top view 16 15 14 13 12 11 10 9 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd s package 24-lead plastic sol t jmax = 110 c, q ja = 130 c/w 24 23 22 21 20 19 18 17 8 7 6 5 4 3 2 1 in ref (msb) d11 d10 d9 d8 d7 clk in clk out hben rd cs busy nc v top view 16 15 14 13 12 11 10 9 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd n package 24-lead plastic dip t jmax = 110 c, q ja = 100 c/w order part number
3 LTC1272 LTC1272-xa LTC1272-xc parameter conditions min typ max min typ max units v ref output voltage (note 6) i out = 0 2.400 2.420 2.440 2.400 2.420 2.440 v v ref output tempco i out = 0 l 5 25 10 45 ppm/ c v ref line regulation 4.75v v dd 5.25v, i out = 0 0.01 0.01 lsb/v v ref load regulation (sourcing current) 0 i out 1ma 2 2 lsb/ma LTC1272-xa/c symbol parameter conditions min typ max units v ih high level input voltage cs, rd, hben, clk in v dd = 5.25v l 2.4 v v il low level input voltage cs, rd, hben, clk in v dd = 4.75v l 0.8 v i in input current cs, rd, hben v in = 0v to v dd l 10 m a input current clk in v in = 0v to v dd l 20 m a v oh high level output voltage all logic outputs v dd = 4.75v i out = C 10 m a 4.7 v i out = C 200 m a l 4.0 v v ol low level output voltage all logic outputs v dd = 4.75v, i out = 1.6ma l 0.4 v i oz high-z output leakage d11-d0/8 v out = 0v to v dd l 10 m a c oz high-z output capacitance (note 7) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma i dd positive supply current cs = rd = v dd , a in = 5v l 15 30 ma p d power dissipation 75 mw accuracy ic dy u w a LTC1272-xa/c symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 10khz input signal 72 db thd total harmonic distortion (up to 5th harmonic) 10khz input signal C 82 db peak harmonic or spurious noise 10khz input signal C 82 db put u i a a u log LTC1272-xa/b/c symbol parameter conditions min typ max units v in input voltage range 4.75v v dd 5.25v l 05v i in input current l 3.5 ma c in input capacitance 50 pf t acq sample-and-hold acquisition time l 0.45 1 m s i ter al refere ce characteristics u u u (note 4) digital a n d dc electrical characteristics u (note 4) (note 4) f sample = 250khz (LTC1272-3), 111khz (LTC1272-8) (note 4)
LTC1272 4 LTC1272-xa/c symbol parameter conditions min typ max units t 1 cs to rd setup time l 0ns t 2 rd to busy delay c l = 50pf 80 190 ns com grade l 230 ns t 3 data access time after rd c l = 20pf 50 90 ns com grade l 110 ns c l = 100pf 70 125 ns com grade l 150 ns t 4 rd pulse width t 3 ns com grade l t 3 ns t 5 cs to rd hold time l 0ns t 6 data setup time after busy 40 70 ns com grade l 90 ns t 7 bus relinquish time 20 30 75 ns com grade l 20 85 ns t 8 hben to rd setup time l 0ns t 9 hben to rd hold time l 0ns t 10 delay between rd operations l 200 ns t 11 delay between conversions 1 m s t 12 aperture delay of sample and hold jitter < 50ps 25 ns t 13 clk to busy delay 80 170 ns com grade l 220 ns t conv conversion time l 12 13 clk cycles cc hara terist ics g ti uw i the l indicates specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together, unless otherwise noted. note 3: when the analog input voltage is taken below ground it will be clamped by an internal diode. this product can handle, with no external diode, input currents of greater than 60ma below ground without latch-up. note 4: v dd = 5v, f clk = 4mhz for LTC1272-3, and 1.6mhz for LTC1272-8, t r = t f = 5ns unless otherwise specified. for best analog performance, the LTC1272 clock should be synchronized to the rd and cs control inputs with at least 40ns separating convert start from the nearest clock edge. note 5: linearity error is specified between the actual end points of the a/d transfer curve. note 6: the LTC1272 has the same 0v to 5v input range as the ad7572 but, to achieve single supply operation, it provides a 2.42v reference output instead of the C5.25v of the ad7572. this requires that the polarity of the reference bypass capacitor be reversed when plugging an LTC1272 into an ad7572 socket. note 7: guaranteed by design, not subject to test. note 8: v dd = 5v. timing specifications are sample tested at 25 c to ensure compliance. all input control signals are specified with t r = t f = 5ns (10% to 90% of 5v) and timed from a voltage level of 1.6v. see figures 13 through 17. (note 8)
5 LTC1272 pin 4 pin 5 pin 6 pin 7 pin 8 pin 9 pin 10 pin 11 pin 13 pin 14 pin 15 pin 16 mnemonic* d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 hben = low db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 hben = high db11 db10 db9 db8 low low low low db11 db10 db9 db8 pi u fu u c u s o ti data bus output, cs and rd = low v ref (pin 2): 2.42v reference output. when plugging into an ad7572 socket, reverse the reference bypass capacitor polarity and short the 10 w series resistor. agnd (pin 3): analog ground. d11 to d4 (pins 4-11): three-state data outputs. dgnd (pin 12): digital ground. d3/11 to d0/8 (pins 13-16): three-state data outputs. clk in (pin 17): clock input. an external ttl/cmos compatible clock may be applied to this pin or a crystal can be connected between clk in and clk out. clk out (pin 18): clock output. an inverted clk in signal appears at this pin. a in (pin 1): analog input, 0v to 5v unipolar input. hben (pin 19): high byte enable input. this pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (d7 to d0/8). see table below. hben also disables conversion starts when high. rd (pin 20): read input. this active low signal starts a conversion when cs and hben are low. rd also enables the output drivers when cs is low. cs (pin 21): the chip select input must be low for the adc to recognize rd and hben inputs. busy (pin 22): the busy output is low when a conver- sion is in progress. nc (pin 23): not connected internally. the LTC1272 does not require negative supply. this pin can accommodate the C15v required by the ad7572 without problems. v dd (pin 24): positive supply, 5v. *d11...d0/8 are the adc data output pins. db11...db0 are the 12-bit conversion results, db11 is the msb. cc hara terist ics uw a t y p i ca lper f o r c e integral nonlinearity code 0 inl error (lsbs) ?.0 1.0 512 1024 4096 LTC1272 ?tpc01 1536 2048 2560 3072 3584 0 v dd = 5v f clk = 4mhz 0 0.5 0.5
LTC1272 6 cc hara terist ics uw a t y p i ca lper f o r c e v ref vs i load (ma) LTC1272 enobs* vs frequency v dd supply current vs minimum clock frequency vs maximum clock frequency vs temperature temperature temperature code 0 inl error (lsbs) ?.0 1.0 512 1024 4096 LTC1272 ?tpc02 1536 2048 2560 3072 3584 0 v dd = 5v f clk = 4mhz 0 0.5 0.5 differential nonlinearity temperature (?) ?5 0 v dd supply current, i dd (ma) 5 10 15 20 25 30 ?5 25 50 125 lt1272 ?tpc03 0 75 100 v dd = 5v f clk = 4mhz temperature (?) ?5 0 clock frequency (khz) 100 200 300 400 500 600 ?5 25 50 125 lt1272 ?tpc04 0 75 100 v dd = 5v temperature (?) ?5 2 clock frequency (mhz) 3 4 5 6 7 8 ?5 25 50 125 lt1272 ?tpc05 0 75 100 i l (ma) ? 2.405 v ref (v) 2.410 2.415 2.420 2.425 2.430 2.435 4 ? ? 2 lt1272 ?tpc06 ? 0 1 f in (khz) 0 0 enobs* 1 4 6 8 10 12 20 60 80 120 lt1272 ?tpc07 40 100 2 3 5 7 9 11 f s = 250khz v dd = 5v *effective number of bits, enobs = s/(n + d) ?1.76db 6.02
7 LTC1272 u s a o pp l ic at i wu u i for atio conversion details conversion start is controlled by the cs, rd and hben inputs. at the start of conversion the successive approxi- mation register (sar) is reset and the three-state data outputs are enabled. once a conversion cycle has begun it cannot be restarted. during conversion, the internal 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in input connects to the sample-and-hold capacitor through a 300 w /2.7k w divider. the voltage divider allows the LTC1272 to convert 0v to 5v input signals while operating from a 4.5v supply. the conver- sion has two phases: the sample phase and the convert phase. during the sample phase, the comparator offset is nulled by the feedback switch and the analog input is stored as a charge on the sample-and-hold capacitor, c sample . this phase lasts from the end of the previous conversion until the next conversion is started. a mini- mum delay between conversions (t 10 ) of 1 m s allows enough time for the analog input to be acquired. during the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. the sample-and-hold capacitor is switched to ground inject- ing the analog input charge onto the comparator summing junction. this input charge is successively compared to binary weighted charges supplied by the capacitive dac. bit decisions are made by the comparator (zero crossing detector) which checks the addition of each successive weighted bit from the dac output. the msb decision is made 50ns (typically) after the second falling edge of clk in following a conversion start. similarly, the succeeding bit decisions are made approximately 50ns after a clk in edge until the conversion is finished. at the end of a conversion, the dac output balances the a in output charge. the sar contents (12-bit data word) which represent the a in input signal are loaded into a 12-bit latch. sample-and-hold and dynamic performance traditionally a/d converters have been characterized by such specs as offset and full-scale errors, integral figure 1. a in input figure 2. LTC1272 non-averaged, 1024 point fft plot. f s = 250khz, f in = 10khz v dac LTC1272 ?ta07 + c dac dac 300 w sample hold c sample 2.7k a in s a r 12-bit latch comparator sample si frequency (khz) 0 ?10 amplitude (db) ?0 ?0 ?0 ?0 ?0 0 20 40 80 120 LTC1272 ?ta23 ?0 ?0 ?0 ?0 ?00 60 100 nonlinearity and differential nonlinearity. these specs are useful for characterizing an adcs dc or low frequency signal performance. these specs alone are not adequate to fully specify the LTC1272 because of its high speed sampling ability. fft (fast fourrier transform) test techniques are used to characterize the LTC1272s frequency response, distor- tion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using a fft algorithm, the LTC1272s spec- tral content can be examined for frequencies outside the fundamental. figure 2 shows a typical LTC1272 fft plot.
LTC1272 8 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the harmonics are limited to the frequency band between dc and one half the sampling frequency. thd is expressed as: 20 log [ ? v 2 2 + v 3 2 + ... + v n 2 /v 1 ] where v 1 is the rms amplitude of the fundamental frequency and v 2 through v n are the amplitudes of the second through nth harmonics. clock and control synchronization for best analog performance, the LTC1272 clock should be synchronized to the cs and rd control inputs as shown in figure 5, with at least 40ns separating convert start from the nearest clk in edge. this ensures that transitions at clk in and clk out do not couple to the analog input and get sampled by the sample-and-hold. the magnitude of this feedthrough is only a few millivolts, but if clk and convert start (cs and rd) are asynchronous, frequency components caused by mixing the clock and convert signals may increase the apparent input noise. when the clock and convert signals are synchronized, small endpoint errors (offset and full-scale) are the most that can be generated by clock feedthrough. even these errors (which can be trimmed out) can be eliminated by ensuring that the start of a conversion (cs and rds falling edge) does not occur within 40ns of a clock edge, as in u s a o pp l ic at i wu u i for atio signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. this includes distortion as well as noise products and for this reason it is sometimes referred to as signal-to-noise + distortion [s/(n + d)]. the output is band limited to frequencies from dc to one half the sampling frequency. figure 2 shows spectral content from dc to 125khz which is 1/2 the 250khz sampling rate. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an a/d and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C1.76]/6.02, where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 250khz the LTC1272 maintains 11.5 enobs or better to 20khz. above 20khz the enobs gradually de- cline, as shown in figure 3, due to increasing second harmonic distortion. the noise floor remains approxi- mately 90db. the dynamic differential nonlinearity re- mains good out to 120khz as shown in figure 4. figure 4. LTC1272 dynamic dnl. f clk = 4mhz, f s = 250khz, f in = 122.25342khz, v cc = 5v figure 3. LTC1272 effective number of bits (enobs) vs input frequency. f s = 250khz code (thousands) 0 error (lsb) ?.0 1.0 14 LTC1272 ?ta24 23 0 0 0.5 0.5 f in (khz) 0 0 enobs* 1 4 6 8 10 12 20 60 80 120 lt1272 ?tpc07 40 100 2 3 5 7 9 11 f s = 250khz v dd = 5v s/(n d) 1 76db
9 LTC1272 u s a o pp l ic at i wu u i for atio figure 5. rd and clk in for synchronous operation LTC1272 ?ta06 cs & rd busy clk in 3 40ns* t 2 t 14 t conv t 13 db0 (lsb) db1 db10 db11 (msb) uncertain conversion time for 30ns < t 14 < 180ns the LTC1272 is also compatible with the ad7572 synchronization modes. * figure 5. nevertheless, even without observing this guide- line, the LTC1272 is still compatible with ad7572 synchro- nization modes, with no increase in linearity error. this means that either the falling or rising edge of clk in may be near rds falling edge. driving the analog input the analog input of the LTC1272 is much easier to drive than that of the ad7572. the input current is not modu- lated by the dac as in the ad7572. it has only one small current spike from charging the sample-and-hold capaci- tor at the end of the conversion. during the conversion the analog input draws only dc current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion is started. any op amp that settles in 1 m s to small current transients will allow maximum speed operation. if slower op amps are used, more settling time can be provided by increasing the time between conversions. suitable de- vices capable of driving the LTC1272 a in input include the lt1006 and lt1007 op amps. internal clock oscillator figure 6 shows the LTC1272 internal clock circuit. a crystal or ceramic resonator may be connected between clk in (pin 17) and clk out (pin 18) to provide a clock oscillator for adc timing. alternatively the crystal/resona- tor may be omitted and an external clock source may be connected to clk in. for an external clock the duty cycle is not critical. an inverted clk in signal will appear at the clk out pin as shown in the operating waveforms of figure 7. capacitance on the clk out pin should be minimized for best analog performance. internal reference the LTC1272 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.42v 1%. it is internally connected to the dac and is also available at pin 2 to provide up to 1ma current to an external load. for minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 m f tantalum in parallel with a 0.1 m f ceramic). a simplified schematic of the reference with its recommended decoupling is shown in figure 8. figure 6. LTC1272 internal clock circuit LTC1272 ?ta09 clk out clk in c1 c2 18 17 1m clock LTC1272 notes: LTC1272-3 ?4mhz crystal/ceramic resonator LTC1272-8 ?1.6mhz crystal/ceramic resonator
LTC1272 10 u s a o pp l ic at i wu u i for atio figure 7. operating waveforms using an external clock source for clk in LTC1272 ?ta08 cs & rd busy clk in 50ns typ db0 (lsb) db1 db10 db11 (msb) clk out LTC1272 ?ta10 + curvature corrected bandgap reference to dac v ref agnd 5v LTC1272 0.1 m f 10 m f 2 3 + figure 8. LTC1272 internal 2.42v reference unipolar operation figure 9 shows the ideal input/output characteristic for the 0v to 5v input range of the LTC1272. the code transitions occur midway between successive integer lsb values (i.e., 1/2lsb, 3/2lsbs, 5/2lsbs . . . fs C 3/2lsbs). the output code is natural binary with 1 lsb = fs/4096 = (5/4096)v = 1.22mv. unipolar offset and full-scale error adjustment in applications where absolute accuracy is important, then offset and full-scale error can be adjusted to zero. offset output code a in , input voltage (in terms of lsbs) 0 00...000 00...001 00...010 00...011 11...110 11...111 1fs lt1272 ?ta11 23 11...101 lsb lsbs lsbs fs ?1lsb fs = 5v 1lsb = fs 4096 full-scale transition figure 9. LTC1272 ideal input/output transfer characteristic error must be adjusted before full-scale error. figure 10 shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset of the op amp driving a in (i.e., a1 in figure 10). for zero offset error apply 0.61mv (i.e., 1/2lbs) at v in and adjust the op amp offset voltage until the adc output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error apply an analog input of 4.99817v (i.e., fs C 3/2lsbs or last code transition) at v in and adjust r1 until the adc output code flickers between 1111 1111 1110 and 1111 1111 1111.
11 LTC1272 u s a o pp l ic at i wu u i for atio the foil width for these tracks should be as wide as possible. noise: input signal leads to a in and signal return leads from agnd (pin 3) should be kept as short as possible to minimize input noise coupling. in applications where this is not possible, a shielded cable between source and adc is recommended. also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. in applications where the LTC1272 data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get lsb errors in conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion (see slow memory mode interfacing), or by using three-state buffers to isolate the LTC1272 data bus. timing and control conversion start and data read operations are controlled by three LTC1272 digital inputs; hben, cs and rd. figure 12 shows the logic structure associated with these inputs. the three signals are internally gated so that a logic 0 is required on all three inputs to initiate a conversion. once initiated it cannot be restarted until conversion is com- plete. converter status is indicated by the busy output, and this is low while conversion is in progress. LTC1272 ?ta13 a in agnd v ref v dd dgnd LTC1272 digital system c1 c2 c3 c4 + analog ground plane ground connection to digital circuitry analog input circuitry 3 2 24 12 1 figure 11. power supply grounding practice application hints wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the LTC1272 a printed circuit board is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the LTC1272. the analog input should be screened by agnd. a single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (agnd) or as close as possible to the LTC1272, as shown in figure 11. pin 12 (LTC1272 dgnd) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be connected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and r3 15 w LTC1272 ?ta12 + a in agnd r2 20k r1 200 w v in 0v to 5v analog input a1 lt1007 *additional pins omitted for clarity LTC1272 1 3 figure 10. unipolar 0v to 5v operation with gain error adjust
LTC1272 12 u s a o pp l ic at i wu u i for atio LTC1272 ?ta14 busy flip flop clear q d 19 21 20 active high active high enable three-state outputs d11....d0/8 = db11....db0 enable three-state outputs d11....d8 = db11....db8 d7....d4 = low d3/11....d0/8 = db11....db8 conversion start (rising edge trigger) 5v hben cs rd LTC1272 d11....d0/8 are the adc data output pins db11....db0 are the 12-bit conversion results figure 12. internal logic for control inputs cs, rd and hben the second is the rom mode which does not require microprocessor wait states. a read operation brings cs and rd low which initiates a conversion and reads the previous conversion result. there are two modes of operation as outlined by the timing diagrams of figures 13 to 17. slow memory mode is designed for microprocessors which can be driven into a wait state, a read operation brings cs and rd low which initiates a conversion and data is read when conversion is complete. table 1. data bus output, cs and rd = low pin 4 pin 5 pin 6 pin 7 pin 8 pin 9 pin 10 pin 11 pin 13 pin 14 pin 15 pin 16 data outputs* d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 hben = low db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 hben = high db11 db10 db9 db8 low low low low db11 db10 db9 db8 note: *d11 . . . d0/8 are the adc data output pins db11 . . . db0 are the 12-bit conversion results, db11 is the msb LTC1272 ?ta15 cs & rd busy clk in 3 40ns* t 2 t 14 t conv t 13 db0 (lsb) db1 db10 db11 (msb) uncertain conversion time for 30ns < t 14 < 180ns the LTC1272 is also compatible with the ad7572 synchronization modes. see ?igital interface?text. * figure 13. rd and clk in for synchronous operation
13 LTC1272 u s a o pp l ic at i wu u i for atio data format the output data format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit microprocessors. data is always right justified (i.e., lsb is the most right-hand bit in a 16-bit word). for a two byte read, only data outputs d7. . . d0/8 are used. byte selection is governed by the hben input which controls an internal digital multiplexer. this multiplexes the 12 bits of conversion data onto the lower d7. . . d0/8 outputs (4msbs or 8lsbs) where it can be read in two read cycles. the 4msbs always appear on d11 . . . d8 whenever the three-state output drives are turned on. slow memory mode, parallel read (hben = low) figure 14 and table 2 show the timing diagram and data bus status for slow memory mode, parallel read. cs and rd going low triggers a conversion and the LTC1272 acknowledges by taking busy low. data from the previous conversion appears on the three-state data outputs. busy returns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs d11 . . . d0/8. slow memory mode, two byte read for a two byte read, only 8 data outputs d7 . . . d0/8 are used. conversion start procedure and data output status for the first read operation is identical to slow memory mode, parallel read. see figure 15 timing diagram and table 3 data bus status. at the end of conversion the low data byte (db7 . . . db0) is read from the adc. a second read operation with hben high, places the high byte on data outputs d3/11 . . . d0/8 and disables conversion start. note the 4msbs appear on data outputs d11 . . . d8 during the two read operations above. rom mode, parallel read (hben = low) the rom mode avoids placing a microprocessor into a wait state. a conversion is started with a read operation and the 12 bits of data from the previous conversion is available on data outputs d11 . . . d0/8 (see figure 16 and table 4). this data may be disregarded if not required. a second read operation reads the new data (db11 . . . db0) and starts another conversion. a delay at least as long as the LTC1272 conversion time plus the 1 m s minimum delay between conversions must be allowed between read operations. figure 14. slow memory mode, parallel read timing diagram table 2. slow memory mode, parallel read data bus status data outputs d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 read db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 t 1 t 2 t 11 t 10 t 6 t 7 t 5 t 1 t 3 t 12 t conv old data db11-db0 new data db11-db0 track hold data busy rd cs rd LTC1272 ?ta16
LTC1272 14 u s a o pp l ic at i wu u i for atio hold t 12 t 7 track data t 3 t 7 t 3 t 2 t conv t conv t 11 t 1 t 4 t 5 t 4 t 1 t 5 t 2 t 12 old data db11-db0 new data db11-db0 busy rd cs LTC1272 ?ta18 figure 15. slow memory mode, two byte read timing diagram table 3. slow memory mode, two byte read data bus status data outputs d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read db7 db6 db5 db4 db3 db2 db1 db0 second read low low low low db11 db10 db9 db8 figure 16. rom mode, parallel read timing diagram table 4. rom mode, parallel read data bus status data outputs d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read (old data) db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 second read db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 old data db7-db0 new data db7-db0 track hold data busy rd cs rd LTC1272 ?ta17 t 8 t 1 t 2 t 3 t conv t 11 t 9 t 8 t 9 t 5 t 1 t 4 t 5 t 10 t 10 t 6 t 7 t 3 t 7 t 12 t 12 hben new data db11-db8
15 LTC1272 u s a o pp l ic at i wu u i for atio old data db7-db0 new data db11-db8 track hold data busy rd cs rd LTC1272 ?ta19 t 8 t 1 t 2 t 3 t conv t 11 t 9 t 8 t 9 t 5 t 1 t 4 t 5 t 10 t 3 t 7 t 3 t 7 t 12 t 12 hben t 7 t 4 t 1 t 8 t 9 new data db7-db0 t 2 t 4 t 5 figure 17. rom mode, two byte read timing diagram table 5. rom mode, two byte read data bus status data outputs d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read db7 db6 db5 db4 db3 db2 db1 db0 second read low low low low db11 db10 db9 db8 third read db7 db6 db5 db4 db3 db2 db1 db0 rom mode, two byte read as previously mentioned for a two byte read, only data outputs d7 . . . d0/8 are used. conversion is started in the normal way with a read operation and the data output status is the same as the rom mode, parallel read. see figure 17 timing diagram and table 5 data bus status. two more read operations are required to access the new conversion result. a delay equal to the LTC1272 conver- sion time must be allowed between conversion start and the second data read operation. the second read opera- tion, with hben high, disables conversion start and places the high byte (4 msbs) on data outputs d3/11 . . . do18. a third read operation accesses the low data byte (db7 . . . db0) and starts another conversion. the 4 msbs appear on data outputs d11 . . . d8 during all three read operations above. microprocessor interfacing the LTC1272 is designed to interface with microproces- sors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. the hben input serves as a data byte select for 8-bit processors and is normally connected to the micropro- cessor address bus. mc68000 microprocessor figure 18 shows a typical interface for the mc68000. the LTC1272 is operating in the slow memory mode. assum- ing the LTC1272 is located at address c000, then the following single 16-bit move instruction both starts a conversion and reads the conversion result: move.w $c000,d0
LTC1272 16 u s a o pp l ic at i wu u i for atio data bus LTC1272 ?ta20 address bus d0 d11 r/w dtack as a1 a23 mc68000 address decode en d0/8 d11 rd busy cs hben LTC1272 additional pins omitted for clarity figure 18. LTC1272 mc68000 interface is accomplished with the single 16-bit load instruction below. for the 8085a lhld (b000) for the z80 ldhl, (b000) this is a two byte read instruction which loads the adc data (address b000) into the hl register pair. during the first read operation, busy forces the microprocessor to wait for the LTC1272 conversion. no wait states are inserted during the second read operation when the mi- croprocessor is reading the high data byte. tms32010 microcomputer figure 20 shows an LTC1272 tms32010 interface. the LTC1272 is operating in the rom mode. the interface is designed for a maximum tms32010 clock frequency of 18mhz but will typically work over the full tms32010 clock frequency range. the LTC1272 is mapped at a port address. the following i/o instruction starts a conversion and reads the previous conversion result into data memory. in a,pa (pa = port address) when conversion is complete, a second i/o instruction reads the up-to-date data into memory and starts another conversion. a delay at least as long as the adc conversion time must be allowed between i/o instructions. at the beginning of the instruction cycle when the adc address is selected, busy and cs assert dtack, so that the mc68000 is forced into a wait state. at the end of conversion busy returns high and the conversion result is placed in the d0 register of the microprocessor. 8085a, z80 microprocessor figure 19 shows a LTC1272 interface for the z80 and 8085a. the LTC1272 is operating in the slow memory mode and a two byte read is required. not shown in the figure is the 8-bit latch required to demultiplex the 8085a common address/data bus. a0 is used to assert hben, so that an even address (hben = low) to the LTC1272 will start a conversion and read the low data byte. an odd address (hben = high) will read the high data byte. this data bus LTC1272 ?ta21 address bus d0 d7 rd wait mreq a0 a15 z80 8085a address decode en d0/8 d7 rd busy cs hben linear circuitry omitted for clarity LTC1272 a0 figure 19. LTC1272 8085a/z80 interface data bus LTC1272 ?ta22 port address bus d0 d11 den pa0 pa2 tms32010 address decode en d0/8 d11 rd cs hben LTC1272 linear circuitry omitted for clarity figure 20. LTC1272 tms32010 interface
17 LTC1272 u s a o pp l ic at i wu u i for atio compatibility with the ad7572 figure 21 shows the simple, single 5v configuration recommended for new designs with the LTC1272. if an ad7572 replacement or upgrade is desired, the LTC1272 can be plugged into an ad7572 socket with minor modi- fications. it can be used as a replacement or to upgrade with sample-and-hold, single supply operation and re- duced power consumption. the LTC1272, while consuming less power overall than the ad7572, draws more current from the 5v supply (it draws no power from the C15v supply). also, a 1 m s minimum time between conversions must be provided to allow the sample-and-hold to reacquire the analog input. figure 22 shows that if the clock is synchronous with cs and rd, it is only necessary to short out the 10 w series resistor and reverse the polarity of the 10 m f bypass capacitor on the v ref pin. the C15v supply is not required and can be removed, or, because there is no internal connection to pin 23, it can remain unmodified. the clock can be considered synchronous with cs and rd in cases where the LTC1272 clk in signal is derived from the same clock as the microprocessor reading the LTC1272. 10 f m in ref d11 (msb) d10 d9 d8 d7 clk in clk out hben rd cs busy nc v LTC1272 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd m p control lines m 0.1 f* 5v 8 or 12-bit parallel bus analog input (0v to 5v) 10 m f 0.1 m f * for grounding and bypassing hints see figure 11 and application hints section * LTC1272 ?ta03 + + 2.42v v output ref figure 21. single 5v supply, 3 m s, 12-bit sampling adc
LTC1272 18 u s a o pp l ic at i wu u i for atio if the clock signal for the ad7572 is derived from a separate crystal or other signal which is not synchronous with the microprocessor clock, then the signals need to be synchronized for the LTC1272 to achieve best analog performance (see clock and control synchronization). the best way to synchronize these signals is to drive the clk in pin of the LTC1272 with a derivative of the processor clock, as mentioned above and shown in figure 22. another way, shown in figure 23, is to use a flip-flop to synchronize the rd to the LTC1272 with the clk in signal. this method will work but has two disavantages over the first: because the rd is delayed by the flip-flop, the actual conversion start and the enabling of the LTC1272s busy and data outputs can take up to one clk in cycle to respond to a rd convert command from the processor. the sampling of the analog input no longer occurs at the processors falling rd edge but may be delayed as much as one clk in cycle. although the LTC1272 will still exhibit excellent dc performance, the flip-flop will introduce jitter into the sampling which may reduce the usefulness of this method for ac systems. 10 f m in ref d11 (msb) d10 d9 d8 d7 clk in** clk out hben rd cs busy nc v LTC1272 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd = p control lines m m 0.1 f ?5v p data bus analog input (0v to 5v) 10 m f 0.1 m f the LTC1272 has the same 0v to 5v input range but provides a 2.42v reference output as opposed to the 5.25v of the ad7572. for proper operation, reverse the reference capacitor polarity and short out the 10 resistor. w * the adc clock should be synchronized to the conversion start signals (cs, rd) or 1-2 lsbs of output code noise may occur. deriving the adc clock from the p clock is adequate. ** the LTC1272 can accommodate the ?5v supply of the ad7572 but does not require it. pin 23 of the LTC1272 is not internally connected. LTC1272 ?ta04 2.42v v output * ref 10 w + 10 f m m 0.1 f 5v + m = m * + ? figure 22. plugging the LTC1272 into an ad7572 socket case 1: clock synchronous with cs and rd
19 LTC1272 figure 23. plugging the LTC1272 into an ad7572 socket case 2: clock not synchronous with cs and rd u s a o pp l ic at i wu u i for atio external asynchronous clock 10 f m in ref d11 (msb) d10 d9 d8 d7 clk in clk out hben rd cs busy nc v LTC1272 d6 d5 d4 dgnd d3/11 d2/10 d1/9 d0/8 a v agnd dd = p control lines m m 0.1 f ?5v p data bus analog input (0v to 5v) 10 m f the LTC1272 has the same 0v to 5v input range but provides a 2.42v reference output as opposed to the 5.25v of the ad7572. for proper operation, reverse the reference capacitor polarity and short out the 10 resistor. w * the d flip-flop synchronizes the conversion start signal (rd ) to the adc clk signal to prevent output code noise which occurs with an asynchronous clock. ** the LTC1272 can accommodate the ?5v supply of the ad7572 but does not require it. pin 23 of the LTC1272 is not internally connected. LTC1272 ?ta05 2.42v v output * ref 10 w 0.1 m f + 10 f m m 0.1 f 5v + = out t 74hc04 rd s q d** clk t 1/2 74hc74 or m + * ? information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1272 20 ? linear technology corporation 1994 u package d e sc r i pti o lt/gp 0694 5k rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 n package 24-lead plastic dip dimensions in inches (millimeters) unless otherwise noted. n24 0594 0.260 ?0.010* (6.604 ?0.254) 1.265* (32.131) 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.015 (0.381) min 0.125 (3.175) min 0.130 ?0.005 (3.302 ?0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 ?0.003 (0.457 ?0.076) 0.050 ?0.085 (1.27 ?2.159) 0.100 ?0.010 (2.540 ?0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protursions shall not exceed 0.010 inch (0.254mm). sol24 0392 note 1 0.598 ?0.614 (15.190 ?15.600) (note 2) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) 0??8?typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) (note 2) 45 0.010 ?0.029 (0.254 ?0.737) 0.005 (0.127) rad min note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. 2. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). so package 24-lead plastic sol

▲Up To Search▲

Price & Availability of LTC1272

	To Download LTC1272 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .